Published On: January 2, 2022

Photo by Denys Nevozhai on Unsplash Advanced semiconductor package technologies have always played a crucial role in transistor scaling. It is also the primary reason these two scaling methods complement each other to enable customers (and industry) with innovative solutions. Die and package level innovation have always provided the industry with solutions (chiplets, heterogeneous integration, big.LITTLE, etc.) that took the semiconductor design and manufacturing to a new level. Today, this synchronized work of die level-scaling with package innovation has taken the semiconductor industry towards a sub-1nm technology node. Historically, the semiconductor industry has always focused on transistor scaling from two points of view: Die: Shrinking the devices while not compromising on the power delivery. Package: Package level scaling (SiP as an example) solution is used to tackle transistor scaling bottlenecks. Similar to […]